Multi-processor systems are now commonly used in environments such as businesses and research. When a processor in a multiprocessor system requests access to the memory, an arbiter is typically utilized to determine which data request is granted and in which order. These requests from the processors and grants from the arbiter are typically carried by the system bus.
Information is typically marked either "cacheable", "cache inhibited", or "writethrough". If information is marked cacheable, then the data can be stored within a cache, rather than having to be transferred to the system memory. If, however, the information is marked cache inhibited, then the data can not go into cache and must be transferred elsewhere, such as system memory. An example of an application which frequently utilizes cache inhibited store instructions is graphics applications. If the information is marked write-through, then the information will go to its destination as well as to the caches. Some of the cache inhibited or write-through information will typically be strictly ordered bus operations.
Computer systems using PowerPC.TM. processors must insure that strictly ordered bus operations are issued to the receiving device in the exact same order of execution from the processor. Computer systems using Amazon PowerPC.TM. may require strict ordering for all operations.
Traditional bus interface unit (BIU) design will cue up strictly ordered bus operations, such as cache inhibited stores, request the bus for an address and data transfer, issue the first bus operation when granted the bus, and wait for a response If the address was accepted (not retried), and the data has already been transferred, then the BIU will request the bus for the next ordered bus operation. The number of cycles that the BIU must wait for a response is typically system dependent. However, the delay between the transferring of ordered bus operations directly translate into less than optimal performance. Additionally, a system may attain higher industry standard benchmarks if the system can achieve good throughput of the ordered bus operations.
Accordingly, what is needed is a system and method for high speed transferring of strictly ordered bus operations. The present invention addresses such a need.